Difference between revisions of "84PCE:Ports:1000"

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(Ports 100A and 1012 only have 4 bits)
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|[[:84PCE:Ports:1002|1002]]
 
|[[:84PCE:Ports:1002|1002]]
 
|06
 
|06
|07
+
|0F
 
|Possibly flash wait states, needs confirmation
 
|Possibly flash wait states, needs confirmation
 
|-
 
|-
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|00
 
|00
 
|FF
 
|FF
|Ports 1009-100F latch value written
+
|Latches value written
 +
|-
 +
|[[:84PCE:Ports:100A|100A]]
 +
|00
 +
|0F
 +
|Latches value written
 +
|-
 +
|[[:84PCE:Ports:100B|100B]]
 +
|00
 +
|FF
 +
|Ports 100B-100F latch value written
 
|-
 
|-
 
|[[:84PCE:Ports:1010|1010]]
 
|[[:84PCE:Ports:1010|1010]]
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|00
 
|00
 
|FF
 
|FF
|Ports 1011-1017 latch value written
+
|Latches value written
 +
|-
 +
|[[:84PCE:Ports:1012|1012]]
 +
|00
 +
|0F
 +
|Latches value written
 +
|-
 +
|[[:84PCE:Ports:1013|1013]]
 +
|00
 +
|FF
 +
|Ports 1013-1017 latch value written
 
|-
 
|-
 
|}
 
|}

Revision as of 10:30, 3 April 2015


Some of these ports have something to do with flash wait states, but no effect on RAM wait states has been observed. At the moment, it seems TI decided to design hardware with a fixed 4-cycle wait on RAM accesses. And it's probably SRAM.

Port    Default    Bits    Information   
1000 01 01 Reset bit 0 to crash. Affects flash wait states.
1001 00 ?? Freeze if write value greater than 3F
1002 06 0F Possibly flash wait states, needs confirmation
1003 00 FF Latches value written
1004 00 FF Latches value written
1005 00 ?? Primary flash wait state control
1006 00 FF Latches value written
1007 FF FF Latches value written
1008 00 01 Latches value written
1009 00 FF Latches value written
100A 00 0F Latches value written
100B 00 FF Ports 100B-100F latch value written
1010 00 01 Latches value written
1011 00 FF Latches value written
1012 00 0F Latches value written
1013 00 FF Ports 1013-1017 latch value written