Difference between revisions of "84PCE:Ports:2000"
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This is the SHA256 chip. It is very similar to [https://hackspire.org/index.php/Memory-mapped_I/O_ports_on_CX#CC000000_-_SHA-256_hash_generator]. The inputs are 32-bit big-endian, but TI fails to compensate for this. | This is the SHA256 chip. It is very similar to [https://hackspire.org/index.php/Memory-mapped_I/O_ports_on_CX#CC000000_-_SHA-256_hash_generator]. The inputs are 32-bit big-endian, but TI fails to compensate for this. | ||
| − | This port is protected. Privileged ports must be unlocked to read and write to these ports. Additionally, flash must be unlocked for the chip to function. | + | This port is protected. Privileged ports must be [[84PCE:Ports:0006#Bit_.5B2.5D|unlocked]] to read and write to these ports. Additionally, flash must be [[84PCE:Ports:0028|unlocked]] for the chip to function. |
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Revision as of 11:57, 1 February 2018
Synopsis
Port Number: 2000-2???
Memory-mapped Address: E10000-E1????
Function: Cryptography
This is the SHA256 chip. It is very similar to [1]. The inputs are 32-bit big-endian, but TI fails to compensate for this. This port is protected. Privileged ports must be unlocked to read and write to these ports. Additionally, flash must be unlocked for the chip to function.
| Ports | Type | Default | Bits | Information |
| 0000 | R/W | 8 | Control | |
| 000C-000F | RO | 3CA2D5EE | 32 | Unknown |
| 0010-004F | R/W | 512 | SHA256 block | |
| 0060-007F | RO | 256 | SHA256 state |
