Difference between revisions of "84PCE:Ports:5000"

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[[Category:84PCE:Ports:By_Address|5000 Range Unknowns]] [[Category:84PCE:Ports:By_Name|5000 Range Unknowns]] [[Category:84PCE:Ports:Unknown|5000 Range Unknowns]]
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[[Category:84PCE:Ports:By_Address|5000 - Interrupt Controller]] [[Category:84PCE:Ports:By_Name|Interrupt Controller]]
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This port range has an interesting semi-pattern of read-only and latching ports. A partial list is below, but ports with some kind of function continue until at least 5055.
+
== Synopsis ==
 +
'''Port Number:''' 5000-505F
 +
 
 +
'''Memory-mapped address:''' F00000
 +
 
 +
'''Function:''' Interrupt Controller
 +
 
 +
This port range is used to configure and control interrupts (appears to be model FTINTC010). There are two sets of interrupt control registers, but only the first actually triggers interrupts on the eZ80.
 +
 
 +
It is arranged in 22-bit bitfields (each occupying a little-endian 32-bit word), with each bit corresponding to a different interrupt source.
 +
 
 +
=== Known Sources ===
 
{|-
 
{|-
−
|<u>Port</u>&nbsp;&nbsp;&nbsp;
+
|<u>Bit</u>&nbsp;&nbsp;&nbsp;
−
|<u>Default</u>&nbsp;&nbsp;&nbsp;
+
|<u>Interrupt Source</u>&nbsp;&nbsp;&nbsp;
−
|<u>Bits</u>&nbsp;&nbsp;&nbsp;
+
−
|<u>Information</u>&nbsp;&nbsp;&nbsp;
+
 
|-
 
|-
−
|[[:84PCE:Ports:5000|5000]]
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|0
−
|00
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|ON Button
−
|??
+
−
|May or may not serve a purpose?
+
 
|-
 
|-
−
|[[:84PCE:Ports:5001|5001]]
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|1
−
|80
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|[[:84PCE:Ports:7000|Timer 1]]
−
|??
+
−
|Bit 2 is set while any key is being pressed
+
 
|-
 
|-
−
|5002
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|2
−
|00
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|[[:84PCE:Ports:7000|Timer 2]]
−
|??
+
−
|''Ports 5002-5003 may always read zero''
+
 
|-
 
|-
−
|[[:84PCE:Ports:5004|5004]]
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|3
−
|11
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|[[:84PCE:Ports:7000|Timer 3]]
−
|FF
+
−
|Reset bit 4 to freeze
+
 
|-
 
|-
−
|[[:84PCE:Ports:5005|5005]]
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|4
−
|30
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|Probably OS timer. Frequency is controlled by bits [1:0] of [[:84PCE:Ports:0000|port 0000]].
−
|FF
+
−
|Setting bit 2 or bit 7 (or both) will freeze the calculator
+
 
|-
 
|-
−
|[[:84PCE:Ports:5006|5006]]
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|10
−
|00
+
|[[:84PCE:Ports:A000|Keyboard]]
−
|3F
+
−
|Latches value written
+
 
|-
 
|-
−
|5007
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|11
−
|00
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|[[:84PCE:Ports:4000|LCD Controller]]
−
|
+
−
|''Ports 5007-500B may always read zero''
+
 
|-
 
|-
−
|[[:84PCE:Ports:500C|500C]]
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|12
−
|19
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|[[:84PCE:Ports:8000|Real-Time Clock]]
−
|FF
+
−
|Reset bit 4 to freeze
+
 
|-
 
|-
−
|[[:84PCE:Ports:500D|500D]]
+
|13
−
|00
+
|[[:84PCE:Ports:3000|USB]]
−
|FF
+
−
|Latches value written
+
 
|-
 
|-
−
|[[:84PCE:Ports:500E|500E]]
+
|15
−
|00
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|Unknown, but signal seems to be constantly on
−
|3F
+
−
|Latches value written
+
 
|-
 
|-
−
|500F
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|16
−
|00
+
|Added in Python Edition.
−
|
+
−
|''Port 500F may always read zero''
+
 
|-
 
|-
−
|[[:84PCE:Ports:5010|5010]]
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|18
−
|00
+
|[[:84PCE:Ports:D000|SPI]]
−
|FF
+
−
|Latches value written
+
 
|-
 
|-
−
|[[:84PCE:Ports:5011|5011]]
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|19
−
|00
+
|Added in Python Edition.
−
|FF
+
−
|Latches value written
+
 
|-
 
|-
−
|[[:84PCE:Ports:5012|5012]]
+
|}
−
|00
+
 
−
|3F
+
=== Registers ===
−
|Latches value written
+
{|-
 +
|<u>Port</u>&nbsp;&nbsp;&nbsp;
 +
|<u>Default</u>&nbsp;&nbsp;&nbsp;
 +
|<u>Bits</u>&nbsp;&nbsp;&nbsp;
 +
|<u>Information</u>&nbsp;&nbsp;&nbsp;
 
|-
 
|-
−
|5013
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|5000
−
|00
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|Read-Only
−
|??
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|003FFFFF
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|''Ports 5013-5020 may always read zero''
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|Raw interrupt status (can be either raw signal or latched on signal change from low-to-high).
 
|-
 
|-
−
|[[:84PCE:Ports:5015|5015]]
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|5004
−
|00
+
|00003011
−
|??
+
|003FFFFF
−
|Read by the boot code at 001327h after power-off?
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|Interrupt enable mask.
 
|-
 
|-
−
|[[:84PCE:Ports:5021|5021]]
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|5008
−
|90
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|Write-Only
−
|??
+
|003FFFFF
−
|Bit 3 is set when a key is held
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|Interrupt acknowledge (used by ISR), seems to only affect latched status bits.
 
|-
 
|-
−
|[[:84PCE:Ports:5022|5022]]
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|500C
−
|08
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|00000019
−
|??
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|003FFFFF
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|Writes do not change value
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|Determines whether bits of [[:84PCE:Ports:5000|5000]] will latch. 0 means raw signal, 1 means latched.
 
|-
 
|-
−
|5023
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|5010
−
|00
+
|00000000
−
|??
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|003FFFFF
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|''Port 5023 may always read zero''
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|Inverts the raw signal of the interrupts corresponding to each 1 bit. Can be used to latch on a high-to-low change.
 
|-
 
|-
−
|[[:84PCE:Ports:5024|5024]]
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|5014
−
|00
+
|Read-only
−
|FF
+
|003FFFFF
−
|Latches value written
+
|Masked interrupt status (used by ISR). Should be equal to ([[:84PCE:Ports:5000|5000]] & [[:84PCE:Ports:5004|5004]]).
 
|-
 
|-
−
|[[:84PCE:Ports:5025|5025]]
+
|5020
−
|00
+
|
−
|FF
+
|
−
|Latches value written
+
|Ports 5020-503F are identical in function to 5000-501F. These registers do not actually trigger interrupts. Since this IP core was meant for use with ARM, these ports were intended to drive the FIQ signal, but the eZ80 has no such alternative interrupts. However, these ports can be used for other purposes such as reading the state of the ON key.
 
|-
 
|-
−
|[[:84PCE:Ports:5026|5026]]
+
|5050
−
|00
+
|Read-only
−
|3F
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|FFFFFFFF
−
|Latches value written
+
|Revision register. Reads 0x00010900 for revision 1.9.0.
 
|-
 
|-
−
|5027
+
|5054
−
|00
+
|Read-only
−
|??
+
−
|''Ports 5027-502B may always read zero''
+
−
|-
+
−
|[[:84PCE:Ports:502C|502C]]
+
−
|00
+
 
|FF
 
|FF
−
|Latches value written
+
|Feature register for input number (IRQ). Reads the number of normal interrupts configured to be handled by the controller, which is 22.
 
|-
 
|-
−
|[[:84PCE:Ports:502C|502D]]
+
|5055
−
|00
+
|Read-only
 
|FF
 
|FF
−
|Latches value written
+
|Feature register for input number (FIQ). Reads the number of FIQ interrupts configured to be handled by the controller, which is 22.
−
|-
+
−
|[[:84PCE:Ports:502C|502E]]
+
−
|00
+
−
|3F
+
−
|Latches value written
+
 
|-
 
|-
 
|}
 
|}

Latest revision as of 14:47, 16 January 2023

Synopsis

Port Number: 5000-505F

Memory-mapped address: F00000

Function: Interrupt Controller

This port range is used to configure and control interrupts (appears to be model FTINTC010). There are two sets of interrupt control registers, but only the first actually triggers interrupts on the eZ80.

It is arranged in 22-bit bitfields (each occupying a little-endian 32-bit word), with each bit corresponding to a different interrupt source.

Known Sources

Bit    Interrupt Source   
0 ON Button
1 Timer 1
2 Timer 2
3 Timer 3
4 Probably OS timer. Frequency is controlled by bits [1:0] of port 0000.
10 Keyboard
11 LCD Controller
12 Real-Time Clock
13 USB
15 Unknown, but signal seems to be constantly on
16 Added in Python Edition.
18 SPI
19 Added in Python Edition.

Registers

Port    Default    Bits    Information   
5000 Read-Only 003FFFFF Raw interrupt status (can be either raw signal or latched on signal change from low-to-high).
5004 00003011 003FFFFF Interrupt enable mask.
5008 Write-Only 003FFFFF Interrupt acknowledge (used by ISR), seems to only affect latched status bits.
500C 00000019 003FFFFF Determines whether bits of 5000 will latch. 0 means raw signal, 1 means latched.
5010 00000000 003FFFFF Inverts the raw signal of the interrupts corresponding to each 1 bit. Can be used to latch on a high-to-low change.
5014 Read-only 003FFFFF Masked interrupt status (used by ISR). Should be equal to (5000 & 5004).
5020 Ports 5020-503F are identical in function to 5000-501F. These registers do not actually trigger interrupts. Since this IP core was meant for use with ARM, these ports were intended to drive the FIQ signal, but the eZ80 has no such alternative interrupts. However, these ports can be used for other purposes such as reading the state of the ON key.
5050 Read-only FFFFFFFF Revision register. Reads 0x00010900 for revision 1.9.0.
5054 Read-only FF Feature register for input number (IRQ). Reads the number of normal interrupts configured to be handled by the controller, which is 22.
5055 Read-only FF Feature register for input number (FIQ). Reads the number of FIQ interrupts configured to be handled by the controller, which is 22.
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