Difference between revisions of "84PCE:Ports:5000"

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(Updated with interrupt controller research)
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[[Category:84PCE:Ports:By_Address|5000 Range Unknowns]] [[Category:84PCE:Ports:By_Name|5000 Range Unknowns]] [[Category:84PCE:Ports:Unknown|5000 Range Unknowns]]
 
[[Category:84PCE:Ports:By_Address|5000 Range Unknowns]] [[Category:84PCE:Ports:By_Name|5000 Range Unknowns]] [[Category:84PCE:Ports:Unknown|5000 Range Unknowns]]
 
This port range has an interesting semi-pattern of read-only and latching ports. Some of these ports have a critical function for interrupt-handling. A partial list is below, but ports with some kind of function continue until at least 5055.
 
This port range has an interesting semi-pattern of read-only and latching ports. Some of these ports have a critical function for interrupt-handling. A partial list is below, but ports with some kind of function continue until at least 5055.
 +
 +
It seems to be arranged in 22-bit bitfields (each occupying a little-endian 32-bit word), with each bit corresponding to a different interrupt source. Known sources so far:
 +
{|-
 +
|<u>Bit</u>&nbsp;&nbsp;&nbsp;
 +
|<u>Interrupt Source</u>&nbsp;&nbsp;&nbsp;
 +
|-
 +
|0
 +
|ON Button
 +
|-
 +
|4
 +
|Unknown, but disabling causes freeze (might be OS timer?)
 +
|-
 +
|10
 +
|Keyboard
 +
|-
 +
|11
 +
|LCD Controller
 +
|-
 +
|15
 +
|Unknown, but signal seems to be constantly on
 +
|-
 +
|}
  
 
This range is (probably?) memory-mapped to F00000.
 
This range is (probably?) memory-mapped to F00000.
Line 11: Line 33:
 
|-
 
|-
 
|[[:84PCE:Ports:5000|5000]]
 
|[[:84PCE:Ports:5000|5000]]
−
|00
+
|Read-Only
−
|??
+
|003FFFFF
−
|May or may not serve a purpose?
+
|Raw interrupt status (can be either raw signal or latched on signal change from low-to-high).
−
|-
+
−
|[[:84PCE:Ports:5001|5001]]
+
−
|80
+
−
|??
+
−
|Bit 2 is set while any key is being pressed
+
−
|-
+
−
|5002
+
−
|00
+
−
|??
+
−
|''Ports 5002-5003 may always read zero''
+
 
|-
 
|-
 
|[[:84PCE:Ports:5004|5004]]
 
|[[:84PCE:Ports:5004|5004]]
−
|11
+
|00003011
−
|FF
+
|003FFFFF
−
|Reset bit 4 to freeze
+
|Interrupt enable mask.
 
|-
 
|-
−
|[[:84PCE:Ports:5005|5005]]
+
|[[:84PCE:Ports:5008|5008]]
−
|30
+
|Write-Only
−
|FF
+
|003FFFFF
−
|Setting bit 2 or bit 7 (or both) will freeze the calculator
+
|Interrupt acknowledge (used by ISR), seems to only affect latched status bits.
−
|-
+
−
|[[:84PCE:Ports:5006|5006]]
+
−
|00
+
−
|3F
+
−
|Latches value written
+
−
|-
+
−
|5007
+
−
|00
+
−
|
+
−
|''Ports 5007-500B may always read zero''
+
 
|-
 
|-
 
|[[:84PCE:Ports:500C|500C]]
 
|[[:84PCE:Ports:500C|500C]]
−
|19
+
|00000019
−
|FF
+
|003FFFFF
−
|Reset bit 4 to freeze
+
|Determines whether bits of [[:84PCE:Ports:5000|5000]] will latch. 0 means raw signal, 1 means latched.
−
|-
+
−
|[[:84PCE:Ports:500D|500D]]
+
−
|00
+
−
|FF
+
−
|Latches value written
+
−
|-
+
−
|[[:84PCE:Ports:500E|500E]]
+
−
|00
+
−
|3F
+
−
|Latches value written
+
−
|-
+
−
|500F
+
−
|00
+
−
|
+
−
|''Port 500F may always read zero''
+
 
|-
 
|-
 
|[[:84PCE:Ports:5010|5010]]
 
|[[:84PCE:Ports:5010|5010]]
−
|00
+
|00000000
−
|FF
+
|003FFFFF
−
|Latches value written
+
|Unknown function.
 
|-
 
|-
−
|[[:84PCE:Ports:5011|5011]]
+
|[[:84PCE:Ports:5014|5014]]
−
|00
+
|Read-only
−
|FF
+
|003FFFFF
−
|Latches value written
+
|Masked interrupt status (used by ISR). Should be equal to ([[:84PCE:Ports:5000|5000]] & [[:84PCE:Ports:5004|5004]]).
 
|-
 
|-
−
|[[:84PCE:Ports:5012|5012]]
+
|5018
−
|00
+
|Read-only
−
|3F
+
|????????
−
|Latches value written
+
|''Ports 5018-501F may always read zero''
 
|-
 
|-
−
|5013
+
|[[:84PCE:Ports:5020|5020]]
−
|00
+
|
−
|??
+
|
−
|''Ports 5013-5020 may always read zero''
+
|Ports 5020-503F seem to be identical in function to 5000-501F (but not mirrors). These registers do not seem to actually trigger interrupts. Assuming this chip was meant for use with ARM, this would likely have been intended to drive the FIQ signal, but the eZ80 has no such alternative interrupts.
−
|-
+
−
|[[:84PCE:Ports:5015|5015]]
+
−
|00
+
−
|??
+
−
|Read by the boot code at 001327h after power-off?
+
−
|-
+
−
|[[:84PCE:Ports:5021|5021]]
+
−
|90
+
−
|??
+
−
|Bit 3 is set when a key is held
+
−
|-
+
−
|[[:84PCE:Ports:5022|5022]]
+
−
|08
+
−
|??
+
−
|Writes do not change value
+
−
|-
+
−
|5023
+
−
|00
+
−
|??
+
−
|''Port 5023 may always read zero''
+
−
|-
+
−
|[[:84PCE:Ports:5024|5024]]
+
−
|00
+
−
|FF
+
−
|Latches value written
+
−
|-
+
−
|[[:84PCE:Ports:5025|5025]]
+
−
|00
+
−
|FF
+
−
|Latches value written
+
−
|-
+
−
|[[:84PCE:Ports:5026|5026]]
+
−
|00
+
−
|3F
+
−
|Latches value written
+
−
|-
+
−
|5027
+
−
|00
+
−
|??
+
−
|''Ports 5027-502B may always read zero''
+
−
|-
+
−
|[[:84PCE:Ports:502C|502C]]
+
−
|00
+
−
|FF
+
−
|Latches value written
+
−
|-
+
−
|[[:84PCE:Ports:502C|502D]]
+
−
|00
+
−
|FF
+
−
|Latches value written
+
−
|-
+
−
|[[:84PCE:Ports:502C|502E]]
+
−
|00
+
−
|3F
+
−
|Latches value written
+
 
|-
 
|-
 
|}
 
|}

Revision as of 00:05, 31 March 2015

This port range has an interesting semi-pattern of read-only and latching ports. Some of these ports have a critical function for interrupt-handling. A partial list is below, but ports with some kind of function continue until at least 5055.

It seems to be arranged in 22-bit bitfields (each occupying a little-endian 32-bit word), with each bit corresponding to a different interrupt source. Known sources so far:

Bit    Interrupt Source   
0 ON Button
4 Unknown, but disabling causes freeze (might be OS timer?)
10 Keyboard
11 LCD Controller
15 Unknown, but signal seems to be constantly on

This range is (probably?) memory-mapped to F00000.

Port    Default    Bits    Information   
5000 Read-Only 003FFFFF Raw interrupt status (can be either raw signal or latched on signal change from low-to-high).
5004 00003011 003FFFFF Interrupt enable mask.
5008 Write-Only 003FFFFF Interrupt acknowledge (used by ISR), seems to only affect latched status bits.
500C 00000019 003FFFFF Determines whether bits of 5000 will latch. 0 means raw signal, 1 means latched.
5010 00000000 003FFFFF Unknown function.
5014 Read-only 003FFFFF Masked interrupt status (used by ISR). Should be equal to (5000 & 5004).
5018 Read-only ???????? Ports 5018-501F may always read zero
5020 Ports 5020-503F seem to be identical in function to 5000-501F (but not mirrors). These registers do not seem to actually trigger interrupts. Assuming this chip was meant for use with ARM, this would likely have been intended to drive the FIQ signal, but the eZ80 has no such alternative interrupts.
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