Difference between revisions of "84PCE:Ports:5000"
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Revision as of 13:59, 5 August 2015
Port Number: 7000-705F
Memory-mapped address: F00000
Function: Interrupt Controller
This port range is used to configure and control interrupts (appears to be model FTINTC010). There are two sets of interrupt control registers, but only the first actually triggers interrupts on the eZ80.
It is arranged in 22-bit bitfields (each occupying a little-endian 32-bit word), with each bit corresponding to a different interrupt source.
|4||Probably OS timer. Frequency is controlled by bits [1:0] of port 0000.|
|15||Unknown, but signal seems to be constantly on|
|5000||Read-Only||003FFFFF||Raw interrupt status (can be either raw signal or latched on signal change from low-to-high).|
|5004||00003011||003FFFFF||Interrupt enable mask.|
|5008||Write-Only||003FFFFF||Interrupt acknowledge (used by ISR), seems to only affect latched status bits.|
|500C||00000019||003FFFFF||Determines whether bits of 5000 will latch. 0 means raw signal, 1 means latched.|
|5010||00000000||003FFFFF||Inverts the raw signal of the interrupts corresponding to each 1 bit. Can be used to latch on a high-to-low change.|
|5014||Read-only||003FFFFF||Masked interrupt status (used by ISR). Should be equal to (5000 & 5004).|
|5020||Ports 5020-503F are identical in function to 5000-501F. These registers do not actually trigger interrupts. Since this IP core was meant for use with ARM, these ports were intended to drive the FIQ signal, but the eZ80 has no such alternative interrupts. However, these ports can be used for other purposes such as reading the state of the ON key.|
|5050||Read-only||FFFFFFFF||Revision register. Reads 0x00010900 for revision 1.9.0.|
|5054||Read-only||FF||Feature register for input number (IRQ). Reads the number of normal interrupts configured to be handled by the controller, which is 22.|
|5055||Read-only||FF||Feature register for input number (FIQ). Reads the number of FIQ interrupts configured to be handled by the controller, which is 22.|