Difference between revisions of "84PCE:Ports:6000"

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(Created page with "6000 - General Purpose Timer General Purpose Timer == Synopsis == '''Port Number:''' 6000-601F '''Functio...")
 
(Renamed to watchdog timer and documented registers)
 
(One intermediate revision by one other user not shown)
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[[Category:84PCE:Ports:By_Address|6000 - General Purpose Timer]] [[Category:84PCE:Ports:By_Name|General Purpose Timer]]
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[[Category:84PCE:Ports:By_Address|6000 - Watchdog Timer]] [[Category:84PCE:Ports:By_Name|Watchdog Timer]]
 
== Synopsis ==
 
== Synopsis ==
 
'''Port Number:''' 6000-601F
 
'''Port Number:''' 6000-601F
  
'''Function:''' General purpose timer
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'''Memory-mapped address:''' F10000
  
This range of ports appears to be the new crystal timer. We seem to have only one.
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'''Function:''' Watchdog timer
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This range of ports is a watchdog timer (appears to be model FTWDT010). Its primary feature is a 32-bit looping downward counter which can be set to either 32768Hz or the CPU frequency. It can also be used to reset the calculator or trigger a non-maskable interrupt (which typically will also reset the calculator). It is unknown whether it can trigger a maskable interrupt.
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== Registers ==
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All registers are little-endian.
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* 6000-6003 (R):
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** 32-bit counter register.
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* 6004-6007 (R/W):
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** 32-bit load register. The counter is loaded with this value when it reaches 0 or the restart register is used.
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* 6008-6009 (W):
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** 16-bit restart register. When the value 5AB9h is written here, the counter is restarted. The bytes can be written individually.
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* 600C (R/W):
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** Bit 0: Timer enable. Set to make the counter count down.
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** Bit 1: System reset enable. Set to reboot the calculator when the counter reaches 0.
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** Bit 2: System reset interrupt enable. Set to trigger a non-maskable interrupt when the counter reaches 0.
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** Bit 3: External signal enable. Set to enable the external signal when the counter reaches 0 (this may have no effect).
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** Bit 4: Clock source. Set to 1 to use the 32768Hz clock, or 0 to use the CPU clock.
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* 6010 (R):
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** Status register. Bit 0 is set after the timer has reached 0, otherwise reset.
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* 6014 (W):
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** Status clear register. Write 1 to reset bit 0 of the status register.
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* 6018 (R/W):
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** 8-bit interrupt length register. Controls the amount of time an interrupt is signaled.
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* 601C-601F (R):
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** 32-bit revision register. Reads a constant 0x00010602, which corresponds to revision 1.6.2.

Latest revision as of 21:51, 3 April 2015

Synopsis

Port Number: 6000-601F

Memory-mapped address: F10000

Function: Watchdog timer

This range of ports is a watchdog timer (appears to be model FTWDT010). Its primary feature is a 32-bit looping downward counter which can be set to either 32768Hz or the CPU frequency. It can also be used to reset the calculator or trigger a non-maskable interrupt (which typically will also reset the calculator). It is unknown whether it can trigger a maskable interrupt.

Registers

All registers are little-endian.

  • 6000-6003 (R):
    • 32-bit counter register.
  • 6004-6007 (R/W):
    • 32-bit load register. The counter is loaded with this value when it reaches 0 or the restart register is used.
  • 6008-6009 (W):
    • 16-bit restart register. When the value 5AB9h is written here, the counter is restarted. The bytes can be written individually.
  • 600C (R/W):
    • Bit 0: Timer enable. Set to make the counter count down.
    • Bit 1: System reset enable. Set to reboot the calculator when the counter reaches 0.
    • Bit 2: System reset interrupt enable. Set to trigger a non-maskable interrupt when the counter reaches 0.
    • Bit 3: External signal enable. Set to enable the external signal when the counter reaches 0 (this may have no effect).
    • Bit 4: Clock source. Set to 1 to use the 32768Hz clock, or 0 to use the CPU clock.
  • 6010 (R):
    • Status register. Bit 0 is set after the timer has reached 0, otherwise reset.
  • 6014 (W):
    • Status clear register. Write 1 to reset bit 0 of the status register.
  • 6018 (R/W):
    • 8-bit interrupt length register. Controls the amount of time an interrupt is signaled.
  • 601C-601F (R):
    • 32-bit revision register. Reads a constant 0x00010602, which corresponds to revision 1.6.2.