Difference between revisions of "84PCE:Ports:E000"

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(Updated based on FTUART010)
(Added divisor latch)
 
Line 17: Line 17:
 
|Read
 
|Read
 
Write
 
Write
|Receive Holding Register
+
 
Transmit Holding Register
+
Read Write
 +
|Receive Holding Register (when bit 7 of E00C is 0)
 +
Transmit Holding Register (when bit 7 of E00C is 0)
 +
 
 +
Divisor Latch LSB (when bit 7 of E00C is 1)
 
|-
 
|-
 
|E004
 
|E004
 
|Read Write
 
|Read Write
|Interrupt Enable Register
+
Read Write
 +
|Interrupt Enable Register (when bit 7 of E00C is 0)
 +
Divisor Latch MSB (when bit 7 of E00C is 1)
 
|-
 
|-
 
|E008
 
|E008

Latest revision as of 12:59, 6 May 2021

Synopsis

Port Number: E000-EFFF

Memory-mapped Address: F90000

Function: ARM Coprocessor

This appears to be an FTUART010 (which is 16550A-compatible), & is connected to the ARM coprocessor on Python Edition. The 16550 register layout (see [1], for example) works after multiplying its offsets by 4.

Port    Direction    Information   
E000 Read

Write

Read Write

Receive Holding Register (when bit 7 of E00C is 0)

Transmit Holding Register (when bit 7 of E00C is 0)

Divisor Latch LSB (when bit 7 of E00C is 1)

E004 Read Write

Read Write

Interrupt Enable Register (when bit 7 of E00C is 0)

Divisor Latch MSB (when bit 7 of E00C is 1)

E008 Read

Write

Interupt Status Register

FIFO Control Register

E00C Read Write Line Control Register
E010 Read Write Modem Control Register
E014 Read Line Status Register
E018 Read Modem Status Register
E01C Read Write Scratchpad Register
E068 Read 01? (not from 16550)
E06C Read 01? (not from 16550)
E070 Read 10? (not from 16550)