86:ASIC
The ASIC used in all known revisions of the TI-86 is an 80-pin QFP with part number T6A43. It contains a Z80-compatible CPU core & additional logic that implements the I/O ports, as well as the LCD Controller. It is also used in some TI-81 revisions, the TI-85, & the PS-6600 Organizer.
CPU
The CPU is a CMOS Z80 clocked around 5-6 MHz depending on the battery level. An extra wait state is automatically inserted during every M1 cycle, so instruction timings need to be adjusted accordingly for timing-critical code. The LCD controller pauses the CPU during DMA using internal /BUSREQ & /BUSACK signals (or some behaviorally-equivalent mechanism), which will not interrupt an M cycle but can occur between M cycles of a single instruction. As a result, behavior that depends on bus content (such as reading from Unused Banks) can be altered by DMA happening in the middle of an instruction. DMA also affects timing-critical code, & can only be disabled by turning the LCD off entirely (via bit 3 of Port 03).
Pinout
The pins are numbered counterclockwise around the ASIC package when viewed from above. Pins 1, 25, 41, & 65 are labeled on the PCB, although the label for 25 is offset from the actual pin due to other components being in the way. These labels are taken from this schematic for the TI-85, since it uses the same ASIC, except where those labels are incorrect. Pins with labels prefixed by a slash (/) are active low. The additional signal names for V1-V15 are taken from the datasheets for the T6A23 column driver & T6A40 row driver on the LCD daughterboard.
| Right side from bottom to top | ||
|---|---|---|
| 1. | A2 | A0-A19 are the address bus. |
| 2. | A1 | |
| 3. | A0 | |
| 4. | D7 | D0-D7 are the data bus. |
| 5. | D6 | |
| 6. | D5 | |
| 7. | D4 | |
| 8. | D3 | |
| 9. | D2 | |
| 10. | D1 | |
| 11. | D0 | |
| 12. | LCDOSCGND | LCD oscillator ground. (Usage of pins 12-14 for the LCD controller clock needs verification.) |
| 13. | LCDOSC1 | |
| 14. | LCDOSC2 | |
| 15. | /ON | |
| 16. | KR0 | KR0-KR7 are keypad rows 0-7, corresponding to the bits of Port 01 when written. |
| 17. | KR1 | |
| 18. | KR2 | |
| 19. | KR3 | |
| 20. | KR4 | |
| 21. | KR5 | |
| 22. | KR6 | |
| 23. | KR7 | |
| 24. | KC0 | KC0-KC7 are keypad columns 0-7, corresponding to the bits of Port 01 when read. |
| Top side from right to left | ||
| 25. | KC1 | |
| 26. | KC2 | |
| 27. | KC3 | |
| 28. | KC4 | |
| 29. | KC5 | |
| 30. | KC6 | |
| 31. | KC7 | |
| 32. | VCC | |
| 33. | V15 | Bit 0 of Port 02 (contrast); V1-V15 are connected to the LCD daughterboard. |
| 34. | V14 | Bit 1 of Port 02 |
| 35. | V13 | Bit 2 of Port 02 |
| 36. | V12 | Bit 3 of Port 02 |
| 37. | V11 | Bit 4 of Port 02 |
| 38. | V10 | (Unknown; apparently contrast-related) |
| 39. | V9 | (Unknown; apparently contrast-related) |
| 40. | V8 | FR (frame): alternates on consecutive frames to ensure LCD drive voltages alternate. |
| Left side from top to bottom | ||
| 41. | V7 | FP (frame pulse) & DIO1: starts a frame. |
| 42. | V6 | LP (latch pulse) & EIO1: starts a row. |
| 43. | V5 | SCP (shift clock pulse): pixel clock. |
| 44. | V4 | DI4; DI1-DI4 are pixel data. |
| 45. | V3 | DI3 |
| 46. | V2 | DI2 |
| 47. | V1 | DI1 |
| 48. | IORQ | External I/O enable; used for Ports 20-3F (active high, unlike the Z80 signal). Apparently also used by prototype TI-86es with flash ROM as the flash chip's output enable signal (needs clarification). |
| 49. | CPUOSCGND | CPU oscillator ground. |
| 50. | CPUOSC1 | |
| 51. | CPUOSC2 | |
| 52. | GND | |
| 53. | /INT | External interrupt request (needs verification); see bit 2 of Port 03. |
| 54. | LP0 | LP0-LP3 are the corresponding bits of Port 07 |
| 55. | LP1 | |
| 56. | LP2 | |
| 57. | LP3 | |
| 58. | /CE0 | /CE0-/CE3 are chip enables for memory banks (see Memory Mapping) |
| 59. | /CE1 | |
| 60. | /CE2 | |
| 61. | /CE3 | |
| 62. | /WE | Write enable. Note that there is no output enable. |
| 63. | A19 | |
| 64. | A18 | |
| Bottom from left to right | ||
| 65. | A17 | |
| 66. | A16 | |
| 67. | A15 | |
| 68. | A14 | |
| 69. | A13 | |
| 70. | A12 | |
| 71. | VCC | |
| 72. | A11 | |
| 73. | A10 | |
| 74. | A9 | |
| 75. | A8 | |
| 76. | A7 | |
| 77. | A6 | |
| 78. | A5 | |
| 79. | A4 | |
| 80. | A3 | |
