Memory on the TI-86 is divided into pages of 16 KiB each. Addresses in the 4000-BFFFh range can be mapped to any page in any bank, while 0000-3FFFh is permanently mapped to ROM page 0, & C000-FFFFh is permanently mapped to RAM page 0.
Bits 0-5 of Port 05 & Port 06 select the page for the 4000-7FFFh & 8000-BFFFh ranges, respectively. These are output on external address lines 14-19 when the corresponding range is accessed. There are 4 memory banks, which can be chosen by bits 6-7 of these ports:
- 00: 256 KiB of ROM, divided into 16 pages. Port bits 4-5 (address bits 18-19) are unused, so ROM repeats 4 times.
- 01: 128 KiB of RAM, divided into 8 pages. Port bits 3-5 (address bits 17-19) are unused, so RAM repeats 8 times.
- 10: Unused.
- 11: Unused on mass-production TI-86es, or mirror of bank 00 on prototype TI-86es with flash ROM. The flash update code uses this bank for writing, in conjunction with bit 6 of Port 04.
Each bank has its own /CE (chip enable) output, while all banks share a common /WE (write enable) output.
The memory mapping when a user program starts has port 05 set to 0Dh (a ROM page containing all the public ROM calls) & port 06 set to 41h (a RAM page containing the operation stack & the floating-point stack). The port 05 value must be restored before returning to the OS, but the port 06 value at exit is ignored.
Writing to ROM or to an unused bank has no effect. Reading from an unused bank will return the current bus content. This is generally the last byte of the instruction doing the reading, unless that instruction is interrupted by LCD DMA, in which case it will be the last byte of the next LCD row to be displayed. However, if the bus is not updated for long enough (by reason of PC being in an unused bank while the LCD is turned off), the bits it reads will gradually decay to 0, causing it to execute various opcodes until it either transfers execution to a normal bank, HALTs, or gets stuck executing NOPs.