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Port Number: 04h

Function: LCD Control, Memory Access Control

This port controls the LCD controller & access to RAM & ROM.

Read Values

Because this port is write-only, its read behavior is the same as Unused Banks.

Write Values

  • Bit 0: Set 0 to enable CPU access to RAM. Set 1 to disable CPU access to RAM, in which case RAM behaves like an unused bank. DMA is still able to read from RAM normally when this bit is 1.
  • Bit 1-2: Number of rows per logical frame. This also affects the LCD interrupt speed.
    • 00: 16 rows & 4X interrupt speed.
    • 01: 32 rows & 2X interrupt speed.
    • 10: 48 rows & 4/3X interrupt speed.
    • 11: 64 rows & normal interrupt speed.
  • Bit 3-4: Number of columns per row to obtain via DMA.
    • 00: 80 columns.
    • 01: 96 columns (used by the TI-81).
    • 10: 128 columns (used by the TI-85 & TI-86).
    • 11: 160 columns (used by the PS-6600).
  • Bit 5: Set 0 to use slower DMA (about 6 cycles per byte). Set 1 to use faster DMA (about 2 cycles per byte).
  • Bit 6: Set 0 to enable writing to flash ROM. Set 1 to disable writing to flash ROM. On mass-production TI-86es, a missing AND gate results in the ROM behaving as if it were an unused bank if this is set to 0.
  • Bit 7: Apparently unused.


  • The OS sets this port to 56h when the calculator is operating normally, & it uses 57h when the CPU is reset & when turning off. This appears to be intended either to save power or to protect the contents of RAM from accidental modification when the main batteries are low or are being changed.
  • Setting fewer than 64 rows causes vertical repetition. It also makes the image darker.
  • Setting fewer than 128 columns per row results in horizontal repetition in a pattern explained by DMA.
  • The OS uses the slower DMA mode. It is unknown whether the faster mode works on all calculators. The numbers of CPU cycles per byte are approximate because the LCD controller uses a separate clock from the CPU clock.
  • Disabling access to RAM from within RAM is not recommended.
  • Disabling access to ROM while the OS interrupt service routine is enabled is not recommended.