Difference between revisions of "Category:84PCE:Ports:By Name"
From WikiTI
KermMartian (Talk | contribs) |
|||
| Line 5: | Line 5: | ||
''Nota bene:'' Port access via IN and OUT is '''prohibited''': IN is censored outside of the OS, and OUT will cause a reset. However, some port ranges are memory-mapped to addresses above E00000, which appears to provide access most desirable port ranges. Security ports, the testing LED, and ports related to master power control seem to be located in the 0000 port range, and are not available through the memory-mapped ranges. | ''Nota bene:'' Port access via IN and OUT is '''prohibited''': IN is censored outside of the OS, and OUT will cause a reset. However, some port ranges are memory-mapped to addresses above E00000, which appears to provide access most desirable port ranges. Security ports, the testing LED, and ports related to master power control seem to be located in the 0000 port range, and are not available through the memory-mapped ranges. | ||
| + | |||
| + | The following page lists port to memory mappings: [[84PCE:Wait_States]] | ||
Latest revision as of 18:13, 7 February 2016
See also list of ports by address
Please read our page on Contributing before editing these pages!
Nota bene: Port access via IN and OUT is prohibited: IN is censored outside of the OS, and OUT will cause a reset. However, some port ranges are memory-mapped to addresses above E00000, which appears to provide access most desirable port ranges. Security ports, the testing LED, and ports related to master power control seem to be located in the 0000 port range, and are not available through the memory-mapped ranges.
The following page lists port to memory mappings: 84PCE:Wait_States
Pages in category "84PCE:Ports:By Name"
The following 30 pages are in this category, out of 30 total.
ABCFG |
G cont.HIKL |
MPRSUW |
