Difference between revisions of "Talk:83Plus:Ports:15"

From WikiTI
Jump to: navigation, search
m (remove me being dumb)
(ld a,i interrupt detection bug: new section)
 
Line 1: Line 1:
 +
== ld a,i interrupt detection bug ==
  
 +
> Also, what does this (ASIC integration of the CPU) mean for the LD A, I/R interrupt-enable-detection bug?
 +
 +
Per testing, nothing, the bug is still present. An early TI-83 Plus with a Z84C00 CPU didn't exhibit the interrupt-enable-detection bug, bewildering everyone present in the chat at the time. Everything else I've tested exhibited that bug.
 +
--[[User:CVSoft|CVSoft]] ([[User talk:CVSoft|talk]]) 00:47, 30 August 2021 (PDT)

Latest revision as of 00:47, 30 August 2021

ld a,i interrupt detection bug

> Also, what does this (ASIC integration of the CPU) mean for the LD A, I/R interrupt-enable-detection bug?

Per testing, nothing, the bug is still present. An early TI-83 Plus with a Z84C00 CPU didn't exhibit the interrupt-enable-detection bug, bewildering everyone present in the chat at the time. Everything else I've tested exhibited that bug. --CVSoft (talk) 00:47, 30 August 2021 (PDT)