Difference between revisions of "84PCE:Ports:1005"
From WikiTI
(RAM wait states update) |
(Updated language to reflect difference between wait states and total time) |
||
| Line 5: | Line 5: | ||
'''Memory-mapped Address:''' E00005 | '''Memory-mapped Address:''' E00005 | ||
| − | '''Function:''' Controls flash wait states. Each read from flash will have at least | + | '''Function:''' Controls flash wait states. Each read from flash will have at least 5 wait states, plus the number of wait states specified in this port. The OS defaults to 04 in this port, so by default, every read from flash incurs a 9 wait state penalty, for a total of 10 clock cycles to read a byte from flash. (V/RAM gets 3 wait states for reads, and 1 waitvstate for writes, for totals of 4 and 2, respectively.) |
== Details == | == Details == | ||
Revision as of 12:12, 5 April 2015
Synopsis
Port Number: 1005
Memory-mapped Address: E00005
Function: Controls flash wait states. Each read from flash will have at least 5 wait states, plus the number of wait states specified in this port. The OS defaults to 04 in this port, so by default, every read from flash incurs a 9 wait state penalty, for a total of 10 clock cycles to read a byte from flash. (V/RAM gets 3 wait states for reads, and 1 waitvstate for writes, for totals of 4 and 2, respectively.)
Details
| Value | Effect |
| 00 | Instant hard crash & reset if OS ISR is enabled |
| 01 | Makes OS a little faster, perhaps 30 % |
| 02-03 | No ill-effects |
| 04 | Normal value |
| 10 | OS feels noticeably sluggish |
| 20 | OS is unbearably sluggish, RAM program dummy loop is not slower |
| FF | Don't even bother trying to do anything |
