Difference between revisions of "Z80 Routines:Optimized:addAtoHL"
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(New page: AddAtoHL AddAtoHL This is an optimized addAtoHL because it is a little faster and doesn't need other 16-bit register. Also it...) |
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[[Category:Z80 Routines:Optimized|AddAtoHL]] | [[Category:Z80 Routines:Optimized|AddAtoHL]] | ||
| + | [[Category:Z80 Routines:Math|AddAtoHL]] | ||
[[Category:Z80 Routines|AddAtoHL]] | [[Category:Z80 Routines|AddAtoHL]] | ||
| − | This is an optimized addAtoHL | + | This is an optimized addAtoHL. It is a little faster and doesn't need another 16-bit register. |
| − | Also it can be changed to add A to any 16-bit register. The only down is | + | |
| + | Also it can be changed to add A to any 16-bit register. The only down side is one extra byte. | ||
| + | |||
| + | Use it as a subroutine (don't forget the ret) or macro. | ||
Normal way: | Normal way: | ||
| Line 13: | Line 17: | ||
</nowiki> | </nowiki> | ||
| + | Alternatives: | ||
<nowiki> | <nowiki> | ||
addAtoHL: | addAtoHL: | ||
add a,l | add a,l | ||
ld l,a | ld l,a | ||
| − | adc a,h ;^ | + | adc a,h ;^ these two lines |
sub l ;v increase h if there is carry | sub l ;v increase h if there is carry | ||
ld h,a | ld h,a | ||
;5 bytes and 20 clock cycles | ;5 bytes and 20 clock cycles | ||
| − | ;but no other 16-bit register | + | ;but no other 16-bit register messed up |
</nowiki> | </nowiki> | ||
Thanks to CoBB. | Thanks to CoBB. | ||
| + | |||
| + | Another alternate way which uses branching and saves 1 T-state on one path (when carrying to h) : | ||
| + | <nowiki> | ||
| + | addAtoHL: | ||
| + | add a,l | ||
| + | ld l,a | ||
| + | jr nc, $+3 | ||
| + | inc h | ||
| + | ;5 bytes, 19/20 clock cycles | ||
| + | </nowiki> | ||
Latest revision as of 00:42, 9 November 2009
This is an optimized addAtoHL. It is a little faster and doesn't need another 16-bit register.
Also it can be changed to add A to any 16-bit register. The only down side is one extra byte.
Use it as a subroutine (don't forget the ret) or macro.
Normal way:
ld d,$00 ld e,a add hl,de ;4 bytes and 22 clock cycles
Alternatives:
addAtoHL: add a,l ld l,a adc a,h ;^ these two lines sub l ;v increase h if there is carry ld h,a ;5 bytes and 20 clock cycles ;but no other 16-bit register messed up
Thanks to CoBB.
Another alternate way which uses branching and saves 1 T-state on one path (when carrying to h) :
addAtoHL: add a,l ld l,a jr nc, $+3 inc h ;5 bytes, 19/20 clock cycles
