Difference between revisions of "Category:84PCE:Ports:By Name"

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Please read our page on [[Contributing]] before editing these pages!
 
Please read our page on [[Contributing]] before editing these pages!
  
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''Nota bene:'' We are '''not''' allowed to access ports directly! If you need any functionality not provided the boot code or OS, ''and'' you don't want to piss off TI, you won't write any software that directly interfaces with the hardware.
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''Nota bene:'' Port access via IN and OUT is '''prohibited''': IN is censored outside of the OS, and OUT will cause a reset. However, some port ranges are memory-mapped to addresses above E00000, which appears to provide access most desirable port ranges. Security ports, the testing LED, and ports related to master power control seem to be located in the 0000 port range, and are not available through the memory-mapped ranges.
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The following page lists port to memory mappings: [[84PCE:Wait_States]]

Latest revision as of 17:13, 7 February 2016

See also list of ports by address

Please read our page on Contributing before editing these pages!

Nota bene: Port access via IN and OUT is prohibited: IN is censored outside of the OS, and OUT will cause a reset. However, some port ranges are memory-mapped to addresses above E00000, which appears to provide access most desirable port ranges. Security ports, the testing LED, and ports related to master power control seem to be located in the 0000 port range, and are not available through the memory-mapped ranges.

The following page lists port to memory mappings: 84PCE:Wait_States

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