Difference between revisions of "84PCE:Ports:1005"
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'''Function:''' Controls flash wait states. Each read from flash will have at least 5 wait states, plus the number of wait states specified in this port. The OS defaults to 04 in this port, so by default, every read from flash incurs a 9 wait state penalty, for a total of 10 clock cycles to read a byte from flash. (V/RAM gets 3 wait states for reads, and 1 waitvstate for writes, for totals of 4 and 2, respectively.) | '''Function:''' Controls flash wait states. Each read from flash will have at least 5 wait states, plus the number of wait states specified in this port. The OS defaults to 04 in this port, so by default, every read from flash incurs a 9 wait state penalty, for a total of 10 clock cycles to read a byte from flash. (V/RAM gets 3 wait states for reads, and 1 waitvstate for writes, for totals of 4 and 2, respectively.) | ||
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| + | This port is only applicable to older devices which feature a [[84PCE:Ports:1000|parallel flash chip.]] | ||
== Details == | == Details == | ||
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| − | |Makes OS a little faster, perhaps 30%. Used by the C toolchain between [https://github.com/CE-Programming/toolchain/commit/76c6620b33c550637e97a8e67ae4e6a788d7d113#diff-acbd510f12643ca0895f22a9f30a5a8cR55 October 2016] and [https://github.com/CE-Programming/toolchain/commit/477efec0f05f530041ff09a31517fc5f92c13047#diff-acbd510f12643ca0895f22a9f30a5a8cL55 April 2017]. Occasional crashes reported on calculators across all revisions (see: fix commit message, [https://tiplanet.org/forum/viewtopic.php?f=8&t=19535 this post]). Not recommended for regular use. | + | |Makes OS a little faster, perhaps 30%. Used by the C toolchain between [https://github.com/CE-Programming/toolchain/commit/76c6620b33c550637e97a8e67ae4e6a788d7d113#diff-acbd510f12643ca0895f22a9f30a5a8cR55 October 2016] and [https://github.com/CE-Programming/toolchain/commit/477efec0f05f530041ff09a31517fc5f92c13047#diff-acbd510f12643ca0895f22a9f30a5a8cL55 April 2017]. Occasional crashes reported on calculators across all revisions (see: [https://github.com/CE-Programming/toolchain/commit/477efec0f05f530041ff09a31517fc5f92c13047 fix commit message], [https://tiplanet.org/forum/viewtopic.php?f=8&t=19535 this post]). Not recommended for regular use. |
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Latest revision as of 07:24, 18 April 2020
Synopsis
Port Number: 1005
Memory-mapped Address: E00005
Function: Controls flash wait states. Each read from flash will have at least 5 wait states, plus the number of wait states specified in this port. The OS defaults to 04 in this port, so by default, every read from flash incurs a 9 wait state penalty, for a total of 10 clock cycles to read a byte from flash. (V/RAM gets 3 wait states for reads, and 1 waitvstate for writes, for totals of 4 and 2, respectively.)
This port is only applicable to older devices which feature a parallel flash chip.
Details
| Value | Effect |
| 00 | Instant hard crash & reset if OS ISR is enabled |
| 01 | Makes OS a little faster, perhaps 30%. Used by the C toolchain between October 2016 and April 2017. Occasional crashes reported on calculators across all revisions (see: fix commit message, this post). Not recommended for regular use. |
| 02 | Used by the C toolchain between April 2016 and October 2016. Insufficient usage data was collected to determine the stability of this value. |
| 03 | Used by the C toolchain since February 2017. No crashes attributed to this value (as of April 2018). |
| 04 | Normal value |
| 10 | OS feels noticeably sluggish |
| 20 | OS is unbearably sluggish |
| FF | Don't even bother trying to do anything |
