Difference between revisions of "84PCE:Ports:1000"
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[[Category:84PCE:Ports:By_Address|1000 Range Unknowns]] [[Category:84PCE:Ports:By_Name|1000 Range Unknowns]] [[Category:84PCE:Ports:Unknown|1000 Range Unknowns]] | [[Category:84PCE:Ports:By_Address|1000 Range Unknowns]] [[Category:84PCE:Ports:By_Name|1000 Range Unknowns]] [[Category:84PCE:Ports:Unknown|1000 Range Unknowns]] | ||
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| + | Some of these ports have something to do with flash wait states, but no effect on RAM wait states has been observed. At the moment, it seems TI decided to design hardware with a fixed 4-cycle wait on RAM accesses. And it's probably SRAM. | ||
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|01 | |01 | ||
|01 | |01 | ||
| − | |Reset bit 0 to crash | + | |Reset bit 0 to crash. Affects flash wait states. |
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|[[:84PCE:Ports:1001|1001]] | |[[:84PCE:Ports:1001|1001]] | ||
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|00 | |00 | ||
|?? | |?? | ||
| − | | | + | |Primary flash wait state control |
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|[[:84PCE:Ports:1006|1006]] | |[[:84PCE:Ports:1006|1006]] | ||
Revision as of 00:15, 3 April 2015
Some of these ports have something to do with flash wait states, but no effect on RAM wait states has been observed. At the moment, it seems TI decided to design hardware with a fixed 4-cycle wait on RAM accesses. And it's probably SRAM.
| Port | Default | Bits | Information |
| 1000 | 01 | 01 | Reset bit 0 to crash. Affects flash wait states. |
| 1001 | 00 | ?? | Freeze if write value greater than 3F |
| 1002 | 06 | 07 | Possibly flash wait states, needs confirmation |
| 1003 | 00 | FF | Latches value written |
| 1004 | 00 | FF | Latches value written |
| 1005 | 00 | ?? | Primary flash wait state control |
| 1006 | 00 | FF | Latches value written |
| 1007 | FF | FF | Latches value written |
| 1008 | 00 | 01 | Latches value written |
| 1009 | 00 | FF | Ports 1009-100F latch value written |
| 1010 | 00 | 01 | Latches value written |
| 1011 | 00 | FF | Ports 1011-1017 latch value written |
