Difference between revisions of "86:ASIC"

Latest revision as of 23:23, 19 June 2023

The ASIC used in all known revisions of the TI-86 is an 80-pin QFP with part number T6A43. It contains a Z80-compatible CPU core & additional logic that implements the I/O ports, as well as the LCD Controller. It is also used in some TI-81 revisions, the TI-85, & the PS-6600 Organizer.

CPU

The CPU is a CMOS Z80 clocked around 5-6 MHz depending on the battery level. An extra wait state is automatically inserted during every M1 cycle, so instruction timings need to be adjusted accordingly for timing-critical code. The LCD controller pauses the CPU during DMA using internal /BUSREQ & /BUSACK signals (or some behaviorally-equivalent mechanism), which will not interrupt an M cycle but can occur between M cycles of a single instruction. As a result, behavior that depends on bus content (such as reading from Unused Banks) can be altered by DMA happening in the middle of an instruction. DMA also affects timing-critical code, & can only be disabled by turning the LCD off entirely (via bit 3 of Port 03).

Pinout

The pins are numbered counterclockwise around the ASIC package when viewed from above. Pins 1, 25, 41, & 65 are labeled on the PCB, although the label for 25 is offset from the actual pin due to other components being in the way. These labels are taken from this schematic for the TI-85, since it uses the same ASIC, except where those labels are incorrect. Pins with labels prefixed by a slash (/) are active low. The additional signal names for V1-V15 are taken from the datasheets for the T6A23 column driver & T6A40 row driver on the LCD daughterboard.