Difference between revisions of "84PCE:Ports:1000"
From WikiTI
(Ports 100A and 1012 only have 4 bits) |
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[[Category:84PCE:Ports:By_Address|1000 Range Unknowns]] [[Category:84PCE:Ports:By_Name|1000 Range Unknowns]] [[Category:84PCE:Ports:Unknown|1000 Range Unknowns]] | [[Category:84PCE:Ports:By_Address|1000 Range Unknowns]] [[Category:84PCE:Ports:By_Name|1000 Range Unknowns]] [[Category:84PCE:Ports:Unknown|1000 Range Unknowns]] | ||
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|01 | |01 | ||
|01 | |01 | ||
− | |Reset bit 0 to crash. | + | |Reset bit 0 to crash. Seems to reduce minimum flash wait states to 2. |
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|[[:84PCE:Ports:1001|1001]] | |[[:84PCE:Ports:1001|1001]] | ||
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|[[:84PCE:Ports:1002|1002]] | |[[:84PCE:Ports:1002|1002]] | ||
|06 | |06 | ||
− | | | + | |07 |
|Possibly flash wait states, needs confirmation | |Possibly flash wait states, needs confirmation | ||
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|00 | |00 | ||
|?? | |?? | ||
− | | | + | |Possibly VRAM access wait states, needs confirmation |
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|[[:84PCE:Ports:1006|1006]] | |[[:84PCE:Ports:1006|1006]] | ||
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|00 | |00 | ||
|FF | |FF | ||
− | | | + | |Ports 1009-100F latch value written |
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|[[:84PCE:Ports:1010|1010]] | |[[:84PCE:Ports:1010|1010]] | ||
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|00 | |00 | ||
|FF | |FF | ||
− | | | + | |Ports 1011-1017 latch value written |
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Revision as of 19:09, 3 April 2015
Port | Default | Bits | Information |
1000 | 01 | 01 | Reset bit 0 to crash. Seems to reduce minimum flash wait states to 2. |
1001 | 00 | ?? | Freeze if write value greater than 3F |
1002 | 06 | 07 | Possibly flash wait states, needs confirmation |
1003 | 00 | FF | Latches value written |
1004 | 00 | FF | Latches value written |
1005 | 00 | ?? | Possibly VRAM access wait states, needs confirmation |
1006 | 00 | FF | Latches value written |
1007 | FF | FF | Latches value written |
1008 | 00 | 01 | Latches value written |
1009 | 00 | FF | Ports 1009-100F latch value written |
1010 | 00 | 01 | Latches value written |
1011 | 00 | FF | Ports 1011-1017 latch value written |