Difference between revisions of "84PCE:Wait States"
Calc84maniac (Talk | contribs) (→Wait State Layout: Meant 1000 for mirror sizes) |
Calc84maniac (Talk | contribs) (Add OS default for Flash) |
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|5+ | |5+ | ||
|Crash | |Crash | ||
| − | |Flash wait states are controlled by [[:84PCE:Ports:1005|1005]], adding to the minimum of 5. | + | |Flash wait states are controlled by [[:84PCE:Ports:1005|1005]], adding to the minimum of 5. The OS sets a total of 9 wait states. |
|- | |- | ||
|400000-7FFFFF | |400000-7FFFFF | ||
Revision as of 20:07, 5 April 2015
Synopsis
The eZ80 processor is able to perform a memory access in a single cycle. However, on the TI-84+CE, accesses will actually take longer due to wait states. For example, a read from RAM will take 4 cycles, because it has 3 wait states. The wait states for Flash accesses can be customized, but it is unknown whether that is the case for other memory regions.
LCD DMA
The LCD controller uses Direct Memory Access to retrieve the pixels from memory. However, since the CPU and the LCD controller cannot access memory at the same time, there are some waitstates caused asynchronously by the DMA. The rate of waitstates caused by the DMA appears to be directly proportional to the rate of data being sent to the screen, so lower bit-per-pixel modes will reduce the general performance hit.
Wait State Layout
| Address Range | Read | Write | Description |
| 000000-3FFFFF | 5+ | Crash | Flash wait states are controlled by 1005, adding to the minimum of 5. The OS sets a total of 9 wait states. |
| 400000-7FFFFF | 257 | Crash | Unmapped address space. Can be mapped to Flash using 1002, after which Flash wait states are active. |
| 800000-CFFFFF | 257 | 257 | Unmapped address space. |
| D00000-D3FFFF | 3 | 1 | RAM |
| D40000-D657FF | 3 | 1 | VRAM |
| D65800-D7FFFF | 3 | 1 | Unmapped address space. Reads garbage. |
| D80000-DFFFFF | 3 | 1 | Mirror of D00000-D7FFFF |
| E00000-E0FFFF | 1 | 1 | Memory-mapped port range 1000 (mirrored every 0100 bytes) |
| E10000-E1FFFF | 1 | 1 | Memory-mapped port range 2000 (reads all zeros) |
| E20000-E2FFFF | 3 | 3 | Memory-mapped port range 3000 (mirrored every 0200 bytes) |
| E30000-E3FFFF | 2 | 1 | Memory-mapped port range 4000 (not mirrored, one contiguous virtual address space) |
| E40000-EFFFFF | 1 | 1 | Unmapped port range (reads all zeros) |
| F00000-F0FFFF | 2 | 2 | Memory-mapped port range 5000 (mirrored every 0100 bytes) |
| F10000-F1FFFF | 2 | 2 | Memory-mapped port range 6000 (mirrored every 0020 bytes) |
| F20000-F2FFFF | 2 | 2 | Memory-mapped port range 7000 (mirrored every 0100 bytes) |
| F30000-F3FFFF | 2 | 2 | Memory-mapped port range 8000 (mirrored every 0080 bytes) |
| F40000-F4FFFF | 2 | 2 | Memory-mapped port range 9000 (mirrored every 1000 bytes, possibly protected port range) |
| F50000-F5FFFF | 2 | 2 | Memory-mapped port range A000 (mirrored every 0080 bytes) |
| F60000-F6FFFF | 2 | 2 | Memory-mapped port range B000 (mirrored every 1000 bytes) |
| F70000-F7FFFF | 2 | 2 | Memory-mapped port range C000 (mirrored every 0100 bytes) |
| F80000-F8FFFF | 2 | 2 | Memory-mapped port range D000 (mirrored every 0080 bytes) |
| F90000-F9FFFF | 2 | 2 | Memory-mapped port range E000 (mirrored every 0080 bytes) |
| FA0000-FAFFFF | 2 | 2 | Memory-mapped port range F000 (reads all zeros) |
| FB0000-FEFFFF | 2 | 2 | Unmapped port range (reads all zeros) |
| FF0000-FFFFFF | 1 | 1 | Unmapped port range (reads all zeros) |
