84PCE:Ports:1005
From WikiTI
Synopsis
Port Number: 1005
Memory-mapped Address: E00005
Function: Controls flash wait states. Each read from flash will have at least 5 wait states, plus the number of wait states specified in this port. The OS defaults to 04 in this port, so by default, every read from flash incurs a 9 wait state penalty, for a total of 10 clock cycles to read a byte from flash. (V/RAM gets 3 wait states for reads, and 1 waitvstate for writes, for totals of 4 and 2, respectively.)
Details
| Value | Effect |
| 00 | Instant hard crash & reset if OS ISR is enabled |
| 01 | Makes OS a little faster, perhaps 30%. Used by the C toolchain between October 2016 and April 2017. Occasional crashes reported on calculators across all revisions. Not recommended for regular use. |
| 02 | Used by the C toolchain between April 2016 and October 2016. Insufficient usage data was collected to determine the stability of this value. |
| 03 | Used by the C toolchain since February 2017. No crashes attributed to this value (as of April 2018). |
| 04 | Normal value |
| 10 | OS feels noticeably sluggish |
| 20 | OS is unbearably sluggish |
| FF | Don't even bother trying to do anything |
