Difference between revisions of "83Plus:Ports:09"
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| − | + | [[Category:83Plus:Ports:By_Address|09 - Link Assist Status/CPU Speed 0 Signaling Rate]] [[Category:83Plus:Ports:By_Name|Link Assist Status/CPU Speed 0 Signaling Rate]] | |
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== Synopsis == | == Synopsis == | ||
| − | '''Port Number:''' | + | '''Port Number:''' 09h |
| − | '''Function:''' | + | '''Function:''' Link Assist Status/CPU Speed 0 Signaling Rate |
| − | This port | + | This port gives information on the status of the hardware link assist. |
=== Read Values === | === Read Values === | ||
| − | * [ | + | * Bit 0: Set if an interrupt was generated by receiving a byte. |
| + | * Bit 1: Set if an interrupt was generated when a byte can be sent. | ||
| + | * Bit 2: Set if an interrupt was generated due to an error in transmission. | ||
| + | * Bit 3: Set if the assist is currently receiving data | ||
| + | * Bit 4: Set if the assist has read a complete byte (which can be read from [[83Plus:Ports:0A|port 0A]]) | ||
| + | * Bit 5: Set if the assist is ready to write data (via [[83Plus:Ports:0D|port 0D]]) | ||
| + | * Bit 6: Set if there was an error during transmission | ||
| + | * Bit 7: Set if the link assist is currently sending a byte. | ||
=== Write Values === | === Write Values === | ||
| − | + | Writing to this port sets the signaling rate of the link assist in CPU speed mode 0 (6 MHz); the link assist uses the same clock as the CPU. Bits 5 through 7 control a divisor to the clock before it reaches the link assist, affecting how fast the link assist can detect changes in the signal states. It will divide by 2^n, allowing you to divide by 1, 2, 4 ... 64. Value 111b (7) will halt the link assist. Bits 0 through 4 control how much time to wait between bits. TI desires a minimum time between bits of 2 microseconds. | |
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== Comments == | == Comments == | ||
| − | + | This port only exists on the 83+ SE and the 84+. | |
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== Credits and Contributions == | == Credits and Contributions == | ||
| − | * ''' | + | * '''Michael Vincent:''' Original documentation of the link assist |
Latest revision as of 20:41, 11 August 2013
Synopsis
Port Number: 09h
Function: Link Assist Status/CPU Speed 0 Signaling Rate
This port gives information on the status of the hardware link assist.
Read Values
- Bit 0: Set if an interrupt was generated by receiving a byte.
- Bit 1: Set if an interrupt was generated when a byte can be sent.
- Bit 2: Set if an interrupt was generated due to an error in transmission.
- Bit 3: Set if the assist is currently receiving data
- Bit 4: Set if the assist has read a complete byte (which can be read from port 0A)
- Bit 5: Set if the assist is ready to write data (via port 0D)
- Bit 6: Set if there was an error during transmission
- Bit 7: Set if the link assist is currently sending a byte.
Write Values
Writing to this port sets the signaling rate of the link assist in CPU speed mode 0 (6 MHz); the link assist uses the same clock as the CPU. Bits 5 through 7 control a divisor to the clock before it reaches the link assist, affecting how fast the link assist can detect changes in the signal states. It will divide by 2^n, allowing you to divide by 1, 2, 4 ... 64. Value 111b (7) will halt the link assist. Bits 0 through 4 control how much time to wait between bits. TI desires a minimum time between bits of 2 microseconds.
Comments
This port only exists on the 83+ SE and the 84+.
Credits and Contributions
- Michael Vincent: Original documentation of the link assist
