Difference between revisions of "83Plus:Ports:27"

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(SE only, no stub)
(reworded a bit, -{{wikify}})
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[[Category:83Plus:Ports:By Address|27 - Block Memory Mapping C000h]]
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[[Category:83Plus:Ports:By Address|27 - Block Memory Mapping C000h]][[Category:83Plus:Ports:By Name|Block Memory Mapping C000h]]
[[Category:83Plus:Ports:By Name|Block Memory Mapping C000h]]
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{{SE-Only Port|07}}
 
{{SE-Only Port|07}}
{{wikify}}
 
 
== Synopsis ==
 
== Synopsis ==
 
'''Port Number:''' 27h
 
'''Port Number:''' 27h
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'''Function:''' Block Memory Mapping C000h
 
'''Function:''' Block Memory Mapping C000h
  
By an order of 64 bytes per block, this port can re-map data from ram page 0 to reflect the memory in C000h - FFFFh no mattter contents of port 5. This port does not map the entire page but only 64 bytes times the value in this port. It maps it starting from high memory (FFFFh) to low.
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By an order of 64 bytes per block, this port can re-map data from ram page 0 to reflect the memory in C000h - FFFFh without regard of the contents of port 5. This port does not map the entire page, but only 64 bytes times the value in this port. It maps it starting from high memory (FFFFh) to low.
  
 
=== Read Values ===
 
=== Read Values ===
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== Comments ==
 
== Comments ==
 
I have no clue why TI thinks it may be necessary to make 1180 bytes from ram page 0 at FB64h, but who knows it could be useful. This also bares more than resemblence to port 28h so I guess they were meant to be used together.
 
I have no clue why TI thinks it may be necessary to make 1180 bytes from ram page 0 at FB64h, but who knows it could be useful. This also bares more than resemblence to port 28h so I guess they were meant to be used together.
 
Wikification is also needed because I believe the name and the description could be confusing. Correct me if I'm wrong. (goes without saying)
 
  
 
== Credits and Contributions ==
 
== Credits and Contributions ==
 
* '''James Montelongo'''
 
* '''James Montelongo'''

Revision as of 19:51, 18 August 2005

This port only exists as a distinct port on the TI-83 Plus Silver Edition, the TI-84 Plus, and the TI-84 Plus Silver Edition. On the standard TI-83 Plus, it acts as a shadow of port 07.

Synopsis

Port Number: 27h

Function: Block Memory Mapping C000h

By an order of 64 bytes per block, this port can re-map data from ram page 0 to reflect the memory in C000h - FFFFh without regard of the contents of port 5. This port does not map the entire page, but only 64 bytes times the value in this port. It maps it starting from high memory (FFFFh) to low.

Read Values

  • This port reads the last value written to it.

Write Values

  • [00h - 12h]: The value times 64 equals the number of bytes that get re-mapped starting from FFFFh. So a vaule of 12h would re-map data in FB80h - FFFFh.
  • [13h - FFh]: Any value 13h or greater will only re-map data in FB64h - FFFFh


Comments

I have no clue why TI thinks it may be necessary to make 1180 bytes from ram page 0 at FB64h, but who knows it could be useful. This also bares more than resemblence to port 28h so I guess they were meant to be used together.

Credits and Contributions

  • James Montelongo