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I've been looking into alot of the hardware and it doesn't look like bit 1 of port 2 is the inverse of the bit 7 of port 10. It looks more like a delay whenever the hardware is used. I compared the values I would get when polled the 2 ports and port 10 gave me quite a bit jitter when it came to the timing. Port 2 on the other hand I got no jitter at all. In fact I wrote to new lcd copy routine, one using port 2 and the other using port 10. On ther 83+(and SE @6mhz) Port 2 version updated faster. On the SE at 15mhz, port 10 version updated faster, while port 2 version was slower than 6mhz test was. Thats enough to clearly say the bits aren't the same, But are used for the same purpose. --Jim e 23:39, 30 Apr 2005 (PDT)

That bit seems to report things other than the LCD status. On the BE, it determines whether the boot code will write to port 5 before writing to port 16. (I have no idea what this means.) FloppusMaximus 12:30, 1 May 2005 (PDT)
I haven't done many tests yet, but I think this bit is always set on the BE. My idea is that on the BE it is some sort of hardware version. When set, the hardware supports per page execution locking (using port 5 and 16). If it isn't set (older calcs maybe, or the flash sim?), the hardware only supports per sector execution locking (port 16 only).
Pages 08-17 can be locked. When per page locking is supported, I'm guessing each bit of port 16 corresponds to a page and bit 0 of port 5 can be used to choose between 08-0F and 10-17. That doesn't explain the other bits of port 5, but like I said, I'm just guessing here anyway. Per sector locking has already been explained on the wiki page. Has that been tested on a real calc? --Kalimero 08:00, 15 Jul 2005 (PDT)