From WikiTI
Jump to: navigation, search

I've been looking into this port a bit more, it seems to control ram execution restriction. Only bits 0,1,4, & 5 do anything. I 'm not exactly sure what the lower nibble does but I have looked into the upper one.

Upper Nibble Page 87 Page 85 Page 83 Page 81
3 Restricted Restricted Restricted Allowed
2 Restricted Restricted Restricted Allowed
1 Restricted Allowed Restricted Allowed
0 Allowed Allowed Allowed Allowed

I post this on the talk page because I don't think there is enough yet and I haven't tested on the 84+SE. Also the 84+ has this port set as 0, yet that seems to crash the 83+se. Hopefully someone has a better clue than me.--Jim e 22:00, 19 Aug 2005 (PDT)

I'm almost positive that for the 256KB chip possibility, mode 3 allows only $81, mode 2 allows $81 and $89, mode 1 allows $81, $85, $89, and $8D, and mode 0 allows all odd pages up to $8F. KermMartian 19:21, 18 April 2013 (UTC)

I said it very sneakily. Unless you specifically know what you are looking for, it won't mean anything to you. If it's too early though, feel free to change it back. --thepenguin77 14:00, 1 October 2011

Er, it's not quite right. 02 does not lock 2C.Dr. D'nar 16:06, 3 October 2011 (UTC)

I have confirmed that there is 8 MB chip support, too, by fiddling with ports 0E, 0F, and 21 on a TI-84+SE. The experiment involved unlocking flash, changing port 21, locking flash, and then seeing whether the certificate was visible with various values of ports 0E and 0F.Dr. D'nar 06:41, 20 February 2013 (UTC)